科技職缺
職缺列表
Senior Design Verification Engineer, Interconnect IP
Senior Design Verification Engineer - Interconnect IP Location: China, Shanghai Time Type: Full time Job Description NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC…
Mixed Signal Design Verification Engineer
Mixed Signal Design Verification Engineer Location: US, MA, Wilmington Time Type: Full time Job Description About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the…
Staff Design Verification Engineer, SoC and eFPGA
Staff Design Verification Engineer – SoC and eFPGA Location: US, CA, San Jose, Rio Robles Time Type: Full time Job Description About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader…
Principal FPGA Image Pipeline Engineer
Principal FPGA Image Pipeline Engineer Location: Goleta, California Remote Type: Not applicable Time Type: Full time Job Description At Alcon, we are driven by the meaningful work we do to help people see brilliantly.…
Principal FPGA Engineer
Principal FPGA Engineer II Location: Goleta, California Remote Type: Not applicable Time Type: Full time Job Description At Alcon, we are driven by the meaningful work we do to help people see brilliantly. We innovate…
Senior NVM Designer
Senior NVM Designer Team: Non-Volatile Memory Location: Palo Alto, CA Commitment: Full-time Workplace Type: onsite Mythic was founded in 2012 by University of Michigan researchers Mike Henry and Dave Fick, who set out…
Senior Design Verification Engineer - Interconnect IP
NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial…
Digital Design Engineer I
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most…
Senior FPGA Design & Verification Engineer – TeraWave
Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re…
FPGA Engineer II (ONSITE)
Date Posted: 2026-08-07

 Country: United States of America

 Location: US-FL-MELBOURNE-313 ~ 1344 S Babcock St ~ BLDG 313

 Position Role Type: Onsite

…
Principal Firmware Engineer
Date Posted: 2026-08-07

 Country: United Kingdom

 Location: Plymouth, Plymouth

 Position Role Type: Hybrid At Collins Aerospace, precision and reliability guide…
Digital Design Engineer I
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most…
Mixed Signal Design Verification (MSDV) Engineer
Mixed Signal Design Verification Engineer Position Summary Integrated Circuit Solutions (ICS) Group is seeking a highly motivated Mixed Signal Design Verification Engineer with a strong background in analog and…
ASIC Design Engineer, STA
The application window is expected to close on: 09/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Join the Cisco Silicon One…
Senior/ IC Design Engineer (Physical Design)
Job Description Perform RTL-to-GDS physical implementation for ASIC IP/subsystem/SoC designs using industry-leading EDA tools and AI-assisted methodologies Develop and execute synthesis, Design-for-Test (DFT), and…
(Sr.) ISP RTL Design Manager
Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements,…
ISP RTL Design Engineer
Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP level and Digital System level Optimize Design for less gate…
(Sr./Staff) ISP RTL Design Engineer
Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements,…
(Sr./Staff) SoC Design Engineer
Description: You would be part of a dynamic digital SoC design team that develops state-of-the-art video processing, neural processing, advanced video analytics accelerators, and the entire Camera Processor SoC. You…