Design Verification engineer/Senior (System Verilog/UVM)

Job Ref: QV79VR4R

Title: Design Verification Engineer

Location: Onsite in HCM City

Requirements:
4+ years experience with Design Verification

Strong experience with SystemVerilog

Strong experience developing test benches with UVM

Strong experience implementing test cases with UVM

Experience with standard interfaces such as I2C, UART, SPI, AMBA, AHB, USB, etc.

Experience with these interfaces is a bonus: PCIe, UCIe, CXL, Ethernet

Contact: Phuong Le - 0903432692 - [email protected]