Hardware - AI Chip Architect
About FuriosaAI
FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea and Silicon Valley, along with a compiler-focused R&D lab in Lisbon.
Our vision is to make AI computing sustainable, enabling access to powerful AI for everyone on Earth. We solve the AI hardware energy and operational cost crisis at the architectural level, rather than through brute force, building the world's first truly AI-native compute platform to unlock the full potential of artificial intelligence for every enterprise.
Key Responsibilities
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Define architecture/microarchitecture specifications. Take ownership of one or more chip modules and implement them in RTL.
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Converge functionality and PPA of the design.
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Implement your designs in RTL (System Verilog or other HDLs) and iterate the design for optimal power, timing, and area.
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Create simple test benches and debug complex logic simulations.
Minimum Qualifications
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Master's degree in Electrical Engineering, Computer Science or equivalent practical experience.
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2+ years of industry experience in chip design, specializing in RTL design (architecture and implementation), logic synthesis, verification, and timing closure
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Experience in microprocessor simulator implementation in depth with C++ or other high-level languages
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Experience in modeling PPA of the design
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Experience in scripting languages to automate simulation and analysis
Preferred Qualifications
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Ph.D in Electrical Engineering, Computer Science or equivalent practical experience is a plus
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Experience in accelerator design is a plus
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Experience with highly pipelined designs, and with multiple-clock-domain designs.
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Knowledge of machine learning algorithms, compiler, processor design, accelerators, and/or memory hierarchies.
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Experience with Chisel or RISC-V is a plus