RTL Design Engineer

Role: (RTL) Design Engineer
Location: Santa Clara, CA (Hybrid negotiable)
Interview: Phone/Skype

We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI #CDC #STA #Synthesis #DFT #Python #TCL #AMBA #PCIe #LowPowerDesign to contribute across design, coding, debugging, and optimization of digital blocks.

#SemiconductorJobs #HardwareDesign #LogicEngineering #RTL #SantaClaraHiring

All your information will be kept confidential according to EEO guidelines.