Senior/Staff Design Verification Engineer
You verify computer arithmetic IPs by developing verification environments, test plans, test cases, formal properties, simulations, regression suites, coverage reports, and automation scripts. You analyze RTL issues, debug waveforms and counterexamples, maintain reusable verification components, and support verification sign-off.
Responsibilities
- Understand the DUT architecture, interfaces, and functional requirements
- Bring up formal verification testbenches and implement constraints and properties
- Run proofs, debug counterexamples, and generate coverage reports
- Define, review, and refine verification test plans
- Implement test cases, stimulus, and test patterns
- Execute simulations and debug RTL issues using waveform-analysis tools
- Run and maintain regression test suites
- Monitor and improve functional and code coverage
- Document test cases, verification results, and coverage reports
- Develop and maintain automation scripts, reusable verification components, and VIP
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or currently pursuing the degree for entry-level roles
- Understanding of digital logic design and RTL development using Verilog or another HDL
- Proficiency with AMBA protocols including AXI, AHB, and APB
- Experience with RTL simulation, debugging, waveform analysis, and EDA tools
- Proficiency with SystemVerilog, UVM, and formal verification tools such as VC Formal or JasperGold
- Familiarity with Linux or Unix and Bash, C Shell, Perl, or Python scripting
- Experience with Git or SVN
- Analytical and debugging skills
- Strong written and verbal English communication skills
- Experience with production-grade IPs, RISC-V, C/C++, coverage-driven verification, or regression automation preferred