Senior Staff Front End Engineer IP Integration

You will implement Verilog RTL for PCIe IP blocks, integrate and configure PCIe IP, evaluate performance, support verification closure and functional coverage, debug pre-silicon and post-silicon issues, and support software development using scripting automation.

Responsibilities

• Implement Verilog RTL for PCIe IP sections
• Integrate and configure PCIe IP
• Evaluate PCIe IP performance
• Support verification closure and functional coverage
• Contribute to design verification and debug pre-silicon and post-silicon issues
• Support software development

Requirements

• Master’s or Bachelor’s degree in Electrical Engineering or Computer Engineering
• Five or more years of semiconductor or high-technology research and development experience
• Verilog RTL development experience with industry-standard tools in an SoC or IP environment
• PCIe IP integration experience
• Strong understanding of PCIe architecture and logic design
• Strong problem-solving and debugging skills
• Ability to use Perl, Shell, or TCL scripting languages

Benefits

• Attractive welfare benefits