Senior Staff Front End Engineer RTL Design

You participate in architecture discussions and design ASIC microarchitectures using Verilog HDL. You conduct design reviews, control delivery quality, select and integrate intellectual property, collaborate with verification and emulation teams, and close designs through synthesis, timing, and power analysis.

Responsibilities

• Participate in architectural design discussions
• Design and implement microarchitectures using Verilog HDL
• Conduct design reviews
• Control delivery quality
• Identify, select, and integrate soft and hard IP
• Collaborate with verification and emulation teams on test plans and debugging
• Collaborate with implementation teams on synthesis, timing, and power closure

Requirements

• Bachelor’s or Master’s degree
• Electrical engineering, computer engineering, or computer science education
• 3 to 5 years of RTL design experience
• ASIC tape-out experience
• Industrial-standard RTL design and delivery flow
• Computer architecture
• VLSI design
• GPGPU, NPU, or CPU module design