Staff Silicon Logical Design Engineer

You will integrate IP and subsystems into top-level SoC designs and develop build and configuration environments. You will perform synthesis, linting, CDC/RDC, and timing checks, support verification and physical design teams, debug integration issues, improve automation flows, produce microarchitecture documentation, and maintain effective communication across sites.

Responsibilities

• Integrate IP and subsystems into top-level SoC designs
• Develop and maintain build and configuration environments
• Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level
• Support verification and physical design teams through interface hand-offs
• Debug and resolve integration issues across hierarchies
• Improve integration flows and automation
• Produce microarchitecture and technical documentation
• Maintain communication between sites

Requirements

• Logical design experience in the semiconductor industry
• 8-12 years of semiconductor industry or product development experience
• Degree in Computer Science, Engineering, or a related subject
• Ability to script in Python or Tcl for automation and design issue resolution
• Experience with SystemVerilog
• Knowledge of digital design flows
• Knowledge of processor design
• Knowledge of application-specific blocks
• Knowledge of high-speed serial interfaces
• Experience with complex third-party IP integration
• Knowledge of arithmetic pipeline design
• Knowledge of floating-point design
• Knowledge of design for test
• Knowledge of synthesis, timing analysis, project planning, and power integrity